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  3. Logic Design Lab

Logic Design Lab

Course ID
CEID_23Υ211
Department
Division of Hardware and Computer Architecture
Professor
ZERVAKIS GEORGIOS
Semester
3
ECTS
2
    -Introduction to the characteristics of BJT and FFT transistors

  • Operation as digital gates and i-v characteristics
    – INTRODUCTION TO DIGITAL ELECTRONICS
  •  Ideal Logic Gates
  • Definitions of logic level and noise margins
  • Dynamic response of logic gates
  • Overview of Boolean algebra
  • NMOS Logic Design
  • Transistor Alternatives to load resistance
  • NMOS Converter Summary and Comparison
  • NMOS NAND and NOR Gates
  • NMOS logic design assembly
  • Dynamic behavior of MOS logic gates
  • PMOS logic
    – COMPLEMENTARY MOS (CMOS) SOFTWARE DESIGN
  •  CMOS Inverter Technology
  • Static characteristics of the CMOS converter
  •  Dynamic Behavior of the CMOS Converter
  •  Power efficiency and power delay in CMOS
  • CMOS NOR and NAND Gates
  • Design of complex gates in CMOS
  • Minimum size portal design and performance
  • Dynamic CMOS Domino logic
  • Cascade Buffers
  • CMOS Latchup
    – MOS MEMORY AND STORAGE CIRCUITS
  • Random access memory
  • Static memory cells
  • Dynamic memory cells
    – Sense Amplifiers
  • Address of decoders
  • Read Only Memory (ROM)
  • Flip-flops
    – Bipolar Logic Circuits
  • The power switch (coupler pair)
  • The Emitter Link Logic Gate (ECL)
  • Noise margin analysis for the ECL gate
  • Apply current source
WebsiteCourse Outline
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